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What's this talk about state machines? I only did explicit state machines in verilog.⏱ 2d↩ 1
The main difference is that in Verilog you're describing hardware registers and combinational logic instead of software running on a CPU. The key difference is that the state variable in Verilog is a flip-flop (hardware), not a variable in RAM. Every clock edge physically updates that register. The biggest mindset shift is that everything in the combinational logic exists simultaneously in hardware, while the state register changes only on the active clock edge. That distinctionβ€”combinational logic versus clocked stateβ€”is fundamental to FPGA and digital hardware design.⏱ 2d↩